NRAM™

Nantero, Inc. is building a high density nonvolatile random access memory chip, which can replace DRAM (dynamic RAM), SRAM (static RAM), flash memory, and ultimately hard disk storage--in other words a universal memory chip suitable for countless existing and new applications in the field of electronics. The target markets in aggregate exceed $100B in revenue per year. Nantero's product is called NRAM™ (Nanotube-based/ Nonvolatile RAM), developed using proprietary concepts and methods derived from leading-edge research in nanotechnology.

NRAM™ engineering samples manufactured in production CMOS fabs have already been shipped to multiple selected customers. The NRAM™ memory is also in development in various customer fabs worldwide for specific product applications by Nantero-licensees. The NRAM™ samples are multimegabit arrays that demonstrate production-ready yield, high speeds (20ns SET/RESET), high reliability (>1000 years at 85C and >10 years at 300°C), extremely low power consumption, and many other attractive characteristics. These NRAM™ samples were designed to provide customers with sufficient data for design of their own Gbit to Tbit-scale standalone and embedded memory products using NRAM™ technology. Nantero's design for NRAM™ involves the use of carbon nanotube-based resistance change elements. Bits are switched between conductive and non-conductive states through the application of write pulses of controlled voltage and current. NRAM™ production uses only standard semiconductor processes, maximizing compatibility with existing semiconductor factories.

NRAM™ will be considerably faster and denser than DRAM, have substantially lower power consumption than DRAM or flash, be as portable as flash memory, and be highly resistant to environmental forces (heat, cold, magnetism). And as a nonvolatile chip, it will provide permanent data storage even without power. Possible uses include the enabling of instant-on computers, which boot and reboot instantly, as well as high-density portable memory - MP3 players with millions of songs, cell phones with terabytes of memory, high-speed network servers and much more. The proprietary NRAM™ design, invented by Dr. Thomas Rueckes, Nantero's Chief Technology Officer, uses carbon nanotubes as the active memory elements. Carbon nanotubes are members of the fullerene family and have amazing properties, including the ability to conduct electricity as well as copper while being stronger than steel and as hard as diamond. Dr. Rueckes' pioneering design takes advantage of these unique properties while cleverly integrating nanotubes with traditional semiconductor technologies for immediate manufacturability.

NRAM Technology
Nantero's NRAM™ technology is based on forming a film of non-woven matrix of carbon nanotubes (CNTs) that are deposited onto a substrate that contains an underlying cell select device and array lines (typically transistors or diodes) that interface the NRAM™ switch. Figure 1 is a SEM image of the deposited film (or fabric) of crossed nanotubes that can be either touching or slightly separated depending on their position.

 
Spin Coated CNT Film

Figure 1
: Spin Coated CNT Film (Top down SEM)
CNTs in the fabric that are in close proximity come under the influence of Van der Waal's interactions resulting in a strong physical adhesion (Eact ~ 5eV) as illustrated in figure 2 allowing electrical conduction between CNTs. CNTs that are separated beyond the Van der Waals interaction distance remain separated due to the high mechanical (~1 TPa) stiffness (Eact>>5 eV) of the CNTs. Being separated, the CNTs are not in electrical contact and do not conduct electrical current between the separated CNTs.
 
Spin Coated CNT Film

Figure 2
: Illustration of CNTs forming an electrical connection
In Nantero's technology, to form a single NRAM™ "cell", each "cell" consists of a number of CNTs forming a network of interlinked CNTs located between two electrodes with one of the electrodes contacting an underlying device such as a transistor and the other electrode to a signal line such a "Select Line" as illustrated in figure 3. The select device and CNT film or fabric located between to the two metal electrodes, which is photolithographically defined and etched, forms the NRAM™ "cell".
 
Spin Coated CNT Film

Figure 3:
NRAM™ "cell" formed CMOS select transistor and NRAM™ resistive change memory element shown in SEM cross-section.
The NRAM™ acts as a resistive non-volatile random access memory NVRAM and can be placed in two or more resistive modes depending on the resistive state of the CNT fabric. When the CNTs are not in contact the resistance state of the fabric is high and represents a "0" state. When the CNTs are brought into contact, the resistance state of the fabric is low and represents a "1" state. What causes the NRAM™ to act as a memory is that the two resistive states of the CNTs are both very stable. In the "OFF" or "0" state, the CNTs or a portion of them as illustrated in figure 4 are not in contact and remain in a separated state due to the stiffness of the CNTs resulting in a high resistance or low current measurement state between the top and bottom electrodes. In the "ON" or "1" nonvolatile state of the device, the CNTs or a portion of them are in contact as illustrated by the yellow pathways of connected switches in figure 4 and remain in a contacted state due to Van der Waals forces between the CNTs resulting in a low resistance or high current measurement state between the top and bottom electrodes. In the "RESET" or "OFF" nonvolatile state there are no electrical pathways, or far fewer such pathways.
 
Spin Coated CNT Film

Figure 4:
Illustration of the conductive paths between the top and bottom electrodes in the NRAM™ fabric.
To switch the NRAM™ between states, a small voltage greater than the read voltage is applied between the top and bottom electrodes. If the NRAM™ is in the "0" state, the voltage applied will cause an electrostatic attraction between the CNTs in close proximity to each other causing a SET operation. After the applied voltage is removed, the CNTs remain in an ON or low resistance state due to physical adhesion (Van der Waals force) with an activation energy (Eact) of approximately 5 eV. If the NRAM™ is in the "1" state, applying a voltage greater than the read voltage across the cell, current will flow across the junctions which generate CNT phonon excitations with sufficient energy to cause separation of the CNT junctions leading to the phonon driven RESET operation. The CNTs remain in the OFF or high resistance state due to the high mechanical stiffness (1 TPa) with an activation energy (Eact) much greater than 5 eV. Figure 5 illustrates both states of an individual pair of CNTs involved in the switch operation. Due to the high activation energy (Eact >/~ 5 eV) required for switching between states, the NRAM™ switch shows excellent resistance to outside interference like radiation and operating temperature that can erase or flip other conventional memories like DRAM.
 
Spin Coated CNT Film

Figure 5:
NRAM™ switching mechanism between low and high resistive states
NRAM™s are fabricated by depositing a uniform layer of CNTs onto a prefabricated array of cell select devices such as transistors as shown in Figure 3. The bottom electrode of the NRAM™ "cell" is in contact with the underlying via connecting the "cell" to the select device. The bottom electrode may be fabricated as part of the underlying via or it may be fabricated simultaneously with the NRAM™ "cell"; e.g., when the "cell" is photolithographically defined and etched. Before the "cell" is photolithographically defined and etched, the top electrode is deposited as a metal film onto the CNT layer so that the top metal electrode is patterned and etched during the definition of the NRAM™ "cell". Following the dielectric passivation and fill of the array, the top metal electrode is exposed by etching back the overlying dielectric, e.g., by CMP (Chemical Mechanical Planarization). With the top electrode exposed, the next level of metal wiring interconnect is fabricated to complete the NRAM™ array. Figure 6 illustrates array lines that can be used to select a single "cell" for writing and reading. Using a cross-grid interconnect arrangement, the NRAM™ and select device, the "cell", forms a memory array similar to other memory arrays such as DRAM or FLASH memories. A single "cell" can be selected by applying the proper voltages to the word line (WL), bit line (BL), and select lines (SL) without disturbing the other "cells" in the array. In some operating modes, select lines (SL) may be connected to a common reference voltage such as ground and only the word line (WL) and bit line (BL) are used.
 
Spin Coated CNT Film

Figure 6:
Typical circuit layout for selecting, writing, and reading a single NRAM™ "cell"

3-D NRAM™ Memory
The semiconductor industry has spent at least a decade of major worldwide engineering efforts at making 3-D semiconductor structures manufacturable. Methods include through-silicon vias (TSV), micro-bumps, silicon interposers, and ball grid array (BGA) solder bumps including testing and handling of known-good-die (KGD). Various assemblies of chip-to-chip stacks, chip-to-interposer interconnections, and other combinations have been fabricated and described at various conferences. Assemblies formed using these methods are sometimes referred to as 2.5-D, almost 3-D, and other such terminology.

In the case of logic, for all but the simplest assemblies, interconnecting and testing integrated chips of various sizes with a large number of input, output, and power and ground terminals present major challenges. In addition, power dissipation remains an unsolved issue. However, for low power memory chips, such as NAND flash chips or NRAM™ resistive memory chips for example, chips sizes are the same and relatively easily interconnected because the input, output, power and ground terminals are the same and relatively low in number. Power dissipation is not an issue and 2.5-D chip stacks have been used in certain limited applications.

 
Spin Coated CNT Film

Figure 7:
NRAM™ cell formed with a CNTFET select transistor shown a gate break away view, and NRAM™ resistive change memory element shown in SEM cross-section

In the case of memory, there are strong market forces pushing for portable, low power, solid state memory and storage devices in the terabyte range. As a result, there is a strong interest in extending the NAND FLASH roadmap to include both chip development in the sub-20 nm range and monolithic 3-D integration, in addition to the more modest 2.5-D stacking options. Monolithic 3-D using NAND semiconductor devices requires complex multiple silicon layers or difficult vertical drilling into the silicon substrate. However, in the case of NRAM™ memories, the storage element formed using carbon nanotubes is decoupled from the semiconductor substrate as illustrated in figure 3. The MOSFET select transistor can be replaced with a carbon nanotube field effect transistor (CNTFET) as illustrated in cross section and by a corresponding CNTFET SEM gate break-away view as illustrated in figure 7. NRAM™ Arrays formed using NRAM™ cells (figure 7) with a combination of CNTFET and CNT fabric storage elements do not require a semiconductor substrate so that multiple levels of NRAM™ arrays can be deposited, separated by insulating layers.

 
Spin Coated CNT Film

Figure 8:
Stacks of NRAM™ arrays 1-N separated by insulating layers and interconnected with underlying CMOS memory control circuits

Figure 8 illustrates a representation of a monolithic 3-D NRAM™ memory with multiple stacked NRAM™ arrays 1-to-N fabricated and interconnected with underlying NRAM™ (memory) circuits. In this example, sense amplifier latches and I/O buffers, as well as control and timing circuits are shown under the NRAM™ array region. Word line drives extend beyond the NRAM™ array region. With most of the memory circuits under the NRAM™ array, the memory footprint is smaller and increases the number of chips-per-wafer, a key measure of memory productivity. And the number of bits per chip can be increased by factors of 2x, 4x, and even more than an order of magnitude, while using existing photolithographic structures and corresponding CMOS devices.

 

 

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